Traditionally, semiconductor chips have been electrically coupled to electrical traces on a substrate via wire interconnects that are soldered on one end to the top active area of the chip and soldered to trace pads on the substrate that surround the chip on the other end. These types of interconnects are not particularly efficient, requiring space for both the surface area of the chip and a perimeter region for the trace pads, resulting in larger chip packages. To more efficiently utilize the substrate surface and facilitate smaller chip packages, the flip chip interconnection process was developed. Essentially, the active surface of the semiconductor chip is flipped over to face the substrate and the chip is soldered directly to trace pads located adjacent to the active surface. The result is a more compact and space-efficient package.
One of the most successful and effective methods of electrically connecting a flipped chip utilizes controlled-collapse chip connection technology (C4). First, solder bumps are applied to pads on the active side of the chip, the substrate or both. Next, the solder bumps are melted and permitted to flow, ensuring that the bumps are fully wetted to the corresponding pads on the chip or substrate. A tacky flux is typically applied to one or both of the surfaces to be joined. The flux-bearing surfaces of the chip and substrate are then placed in contact with each other in general alignment. A reflow is performed by heating the chip and substrate package to or above the solder's melting point. The solder on the chip and the substrate combine and the surface tension of the molten solder causes the corresponding pads to self-align with each other. The joined package is then cooled to solidify the solder. The resulting height of the solder interconnects is determined based on a balance between the surface tension of the molten solder columns and the weight of the chip. Any flux or flux residue is removed from the chip and substrate combination in a defluxing operation. Finally, an epoxy underfill is applied between the bottom surface of the chip and the top surface of the substrate, surrounding and supporting the solder columns. The reliability and fatigue resistance of the chip substrate solder connection is increased significantly. The underfill acts to carry a significant portion of the thermal loads induced by coefficient of thermal expansion (CTE) differences between the chip and substrate, rather than having all the thermal load transferred through the solder columns.